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82C83H
March 1997
CMOS Octal Latching Inverting Bus Driver
Description
The Intersil 82C83H is a high performance CMOS Octal Latching Buffer manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C83H provides an 8bit parallel latch/buffer in a 20 lead pin package. The active high strobe (STB) input allows transparent transfer of data and latches data on the negative transition of this signal. The active low output enable (OE) permits simple interface to microprocessor systems. The 82C83H provides inverted data at the outputs.
Features
* Full 8-Bit Parallel Latching Buffer * Bipolar 8283 Compatible * Three-State Inverting Outputs * Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max * Gated Inputs - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors * Single 5V Power Supply * Low Power Operation - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA * Operating Temperature Ranges - C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC - I82C83H . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC - M82C83H . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
PART NO. CP82C83H IP82C83H CS82C83H IS82C83H CD82C83H ID82C83H MD82C83H/B 8406702RA MR82C83H/B 84067022A SMD# 20 Pad CLCC SMD# 20 Ld CERDIP 20 Ld PLCC PACKAGE 20 Ld PDIP TEMP RANGE 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC 0oC to +70oC -55oC to +125oC -55oC to +125oC -55oC to +125oC PKG. NO E20.3 E20.3 N20.35 N20.35 F20.3 F20.3 F20.3 F20.3 J20.A J20.A
Pinouts
82C83H (PDIP, CERDIP) TOP VIEW
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 OE 1 2 3 4 5 6 7 8 9 20 VCC 19 DO0 18 DO1 17 DO2 16 DO3 15 DO4 14 DO5 13 DO6 12 DO7 11 STB
9 OE 10 GND 11 STB 12 DO7 13 DO6 DI3 DI4 DI5 DI6 DI7 4 5 6 7 8 18 DO1 17 DO2 16 DO3 15 DO4 14 DO5
82C83H (PLCC, CLCC) TOP VIEW
DO0 19 VCC 20 DI2 DI1 2 DI0 1
3
GND 10
TRUTH TABLE STB X H H H = Logic One L = Logic Zero X = Don`t Care OE H L L L DI X L H X DO HI-Z H L PIN DI0 - DI7 DO0 - DO7 STB OE
PIN NAMES DESCRIPTION Data Input Pins Data Output Pins Active High Strobe Active Low Output Enable
HI-Z = High Impedance = Negative Transition = Latched to Value of Last Data
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2971.1
4-281
82C83H Functional Diagram
DI0 DQ CLK DO0
DI1 DI2 DI3 DI4 DI5 DI6 DI7
DO1 DO2 DO3 DO4 DO5 DO6 DO7
state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the transparent mode (STB = logic one). ICC remains below the maximum ICC standby specification of 10A during the time inputs are disabled, thereby greatly reducing the average power dissipation of the 82C8X series devices.
VCC P OE DATA IN VCC P N P INTERNAL DATA N
STB
OE
N
FIGURE 2. 82C86H/87H GATED INPUTS
Gated Inputs During normal system operation of a latch, signals on the bus at the device inputs will become high impedance or make transitions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically cause an increase in power dissipation in CMOS devices by creating a low resistance path between VCC and GND when the signal is at or near the input switching threshold. Additionally, if the driving signal becomes high impedance (float'' condition), it could create an indeterminate logic state at the inputs and cause a disruption in device operation. The Intersil 82C8X series of bus drivers eliminates these conditions by turning off data inputs when data is latched (STB = logic zero for the 82C82/83H) and when the device is disabled (OE = logic one for the 82C86H/87H). These gated inputs disconnect the input circuitry from the VCC and ground power supply pins by turning off the upper P-channel and lower N-channel (See Figures 1 and 2). No current flow from VCC to GND occurs during input transitions and invalid logic states from floating inputs are not transmitted. The next stage is held to a valid logic level internal to the device.
VCC P P STB DATA IN N N P INTERNAL DATA VCC
Decoupling Capacitors
The transient current required to charge and discharge the 300pF load capacitance specified in the 82C83H data sheet is determined by I = CL (dv/dt) Assuming that all outputs change state at the same time and that dv/dt is constant;
(V CC x 80 percent ) I = C L ------------------------------------------------------t t
R F
(EQ. 1)
where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight outputs. I = (8 x 300 x 10-12) x (5.0V x 0.8)/(20 x 10-9) = 480mA This current spike may cause a large negative voltage spike on VCC which could cause improper operation of the device. To filter out this noise, it is recommended that a 0.1F ceramic disc capacitor be placed between VCC and GND at each device, with placement being as near to the device as possible.
ALE MULTIPLEXED BUS ICC ADDRESS ADDRESS
VCC P
VCC
P STB N P INTERNAL DATA N N
N
DATA IN
FIGURE 1. 82C82/83H
D.C. input voltage levels can also cause an increase in ICC if these input levels approach the minimum VIH or maximum VIL conditions. This is due to the operation of the input circuitry in its linear operating region (partially conducting
FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS
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82C83H
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND 0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JAoC/W JCoC/W CERDIP Package . . . . . . . . . . . . . . . . 70 16 CLCC Package . . . . . . . . . . . . . . . . . . 80 20 PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A PLCC Package . . . . . . . . . . . . . . . . . . 75 N/A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65oC to +150oC Max Junction Temperature Ceramic Package . . . . . . . . . . . . . . +175oC Max Junction Temperature Plastic Package. . . . . . . . . . . . . . . . +150oC Lead Temperature (Soldering 10s) (PLCC - Lead Tips Only) . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range C82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC I82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC M82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
VCC = 5.0V 10%; TA = 0oC to +70oC (C82C83H); TA = -40oC to +85oC (I82C83H); TA = -55oC to +125oC (M82C83H) MIN 2.0 2.2 MAX UNITS V TEST CONDITIONS C82C83H, I82C83H, M82C83H, (Note 1)
SYMBOL VIH VIL VOH VOL II IO lCCSB
PARAMETER Logical One Input Voltage
Logical Zero Input Voltage Logical One Output Voltage 3.0 VCC -0.4V
0.8 -
V V IOH = -8mA, IOH = -100mA, OE = GND IOL = 20mA, OE = GND VIN = GND or VCC, DIP Pins 1-9,11 VO = GND or OE VCC -0.5V DIP Pins 12-19 VIN = VCC or GND VCC = 5.5V Outputs Open TA = +25oC, VCC = 5V, Typical (See Note 2)
Logical Zero Output Voltage Input Leakage Current -10
0.45 10
V A A A mA/ MHz
Output Leakage Current
-10
10
Standby Power Supply Current
-
10
IC COP
Operating Power Supply Current
-
1
NOTES: 1. VIH is measured by applying a pulse of magnitude = VlHMIN to one data Input at a time and checking the corresponding device output for a valid logical 1 - during valid input high time. Control pins (STB, CE) are tested separately with all device data input pins at VCC -0.4V. 2. Typical ICCOP = 1 mA/MHz of STB cycle time. (Example: 5MHz P, ALE = 1.25MHz, ICCOP = 1.25mA).
Capacitance
SYMBOL CIN COUT
TA = +25oC PARAMETER Input Capacitance Output Capacitance TYPICAL 13 20 UNITS pF pF TEST CONDITIONS FREQ = 1MHz, all measurements are referenced to device GND
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82C83H
AC Electrical Specifications
VCC = 5.0V 10%; CL = 300pF (Note 1), FREQ = 1MHz TA = 0oC to +70oC (C82C83H); TA = -40oC to +85oC (l82C83H); TA = -55oC to +125oC (M82C83H) LIMITS SYMBOL (1) TlVOV (2) TSHOV (3) TEHOZ (4) TELOV (5) TlVSL (6) TSLIX (7) TSHSL (8) TR, TF NOTES: 1. Output load capacitance is rated 300pF for both ceramic and plastic packages. 2. All AC Parameters tested as per test load circuits. Input rise and tall times are driven at 1ns/V. 3. Input test signals must switch between VIL -0.4V and VlH +0.4V. PARAMETER Propagation Delay Input to Output Propagation Delay STB to Output Output Disable Time Output Enable Time Input to STB Set Up Time Input to STB Hold Time STB High Time Input Rise/Fall Times MIN 5 10 5 10 0 30 15 MAX 25 50 22 45 20 UNITS ns ns ns ns ns ns ns ns TEST CONDITIONS See Notes 2, 3 See Notes 2, 3 See Notes 2, 3 See Notes 2, 3 See Notes 2, 3 See Notes 2, 3 See Notes 2, 3 See Notes 2, 3
Timing Waveforms
TR, TF (8) INPUTS 2.0V 0.8V TIVSL (5) STB TSHSL (7) OE TIVOV (1) OUTPUTS TSHOV (2) TSLIX (6)
TEHOZ (3) VOH -0.1V VOL +0.1V
TELOV (4) 3.0V 0.45V
All Timing measurements are made at 1.5V unless otherwise noted. FIGURE 4. TIMING WAVEFORMS
Test Load Circuits
2.27V 91 OUTPUT TEST POINT 300pF (SEE NOTE) OUTPUT 1.5V 180 TEST POINT 300pF (SEE NOTE)
FIGURE 5. TIVOV, TSHOV
FIGURE 6. TELOV OUTPUT HIGH ENABLE
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82C83H Test Load Circuits
(Continued)
1.5V 51 OUTPUT TEST POINT 300pF (SEE NOTE) OUTPUT
2.27V 91 TEST POINT 50pF (SEE NOTE)
NOTE: Includes jig and stray capacitance. FIGURE 7. TELOV OUTPUT LOW ENABLE FIGURE 8. TEHOZ OUTPUT LOW/HIGH DISABLE
Burn-In Circuits
VCC VCC R4 20 19 18 17 16 15 14 9 10 11 12 13 R4 R4 R4 R4 R4 VCC 2 R4 VCC 2 R4 C1
F2
F2
R4
R4
R1 F2 F2 F2 F2 F2 F2 F2 F2 F0 R1 R1 R1 R1 R1 R1 R1 R1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 R1
C1 A A A A A A A A F1 A R2 VCC R2 F2 F2 F2 F2 F2 R4 R4 R4 R4 R4 4 5 6 7 8
3
2
R3
F0
FIGURE 9. MD82C83H CERDIP NOTES: 1. VCC = 5.5V 0.5V GND = 0V 2. VIH = 4.5V 10% 3. VIL = -0.2 to 0.4V 4. R1 = 47kW 5% 5. R2 = 2.0kW 5% 6. R3 = 1.0kW 5% 7. R4 = 5.0kW 5% 8. C1 = 0.01F Minimum 9. F0 = 100kHz 10% 10. F1 = F0/2, F2 = F1/2, F3 = F2/2
FIGURE 10. MR82C83H CLCC
4-285
F1
R3
R4
VCC
1
F2
2
82C83H Die Characteristics
DIE DIMENSIONS: 138.6 x 155.5 x 19 1 mils METALLIZATION: Type: Silicon - Aluminum Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 2.0 x 105 A/cm2
Metallization Mask Layout
82C83H
DI2
DI1
DI2
VCC
DO0
DO1
DO2
DI3 DI4 DO3
DO4
DI5 DO5 DI6
DI7
OE GND
STB
DO7 DO6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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